FPGA-based Implementation of Compact Compressor and Decompressor of Floating-Point Data-Stream for Bandwidth Reduction

This paper presents FPGA-based implementation and performance analysis of the hardware for lossless compression of a floating-point data stream. The implementation includes the variable-to-fixed length converter (VFCONV) and the fixed-to-variable length converter (FVCONV) that have not been designed and evaluated so far. The prototype system on ALTERA Stratix IV FPGA demonstrates that the compressor and the decompressor are very small so that they each consume only 0.5 % adaptive LUTs of the total resource on the FPGA. The compressor and the decompressor can operate at about 250 MHz and 200 MHz, respectively, while further optimization is still possible. Such small but high-speed hardware modules can reduce the bandwidth by a factor of an average compression ratio. Evaluation with the computational results of 2D fluid simulation shows that the compressor has an average compression ratio of 3.7. This means that the compressor operating at 200 MHz can supply the bandwidth of 800 MB/s for single-precision floating-point numbers with the compressed bandwidth of 216 MB/s.